Embodiments of this disclosure relate generally to semiconductor inspection tools, and more particularly to an inspection algorithm and method for determining mask making quality. Embodiments of this disclosure use a deconvolution algorithm to inspect mask quality by reversing the SEM contours of a mask to polygons of an IC design layout.
In one conventional integrated circuit (IC) inspection model, a post-optical proximity correction (OPC) design pattern is input into a production model that implements a mask process model and a lithography process model to produce a simulated wafer pattern. It may be desirable in certain situations to simulate production of a wafer based on a mask contour generated from the design pattern (e.g., to determine whether a defect in a physical wafer is caused by a masking process). However, a mask contour pattern is not a suitable input to the foregoing production model, because the production model usually lumps the mask process with the lithography process since only wafer data is used during the model calibration. Accordingly, applying certain mask process parameters, such as mask corner rounding, to a mask contour input will generally result in a virtual wafer pattern that exhibits critical dimension (CD) variations due to double counting the mask process effect on the mask contour pattern.
In another embodiment of a conventional IC inspection model, a mask contour pattern is input into a production model that only has a lithography process model. Such a production model may be referred to as a “mask effect-less model” (MELM). However, MELM models require increased calibration efforts. Furthermore, MELM models may not accurately simulate real-world results, particularly because conventional lithography process models cannot assure model accuracy when provided with the irregular (i.e., non-polygon) shapes present in a mask contour pattern. Accordingly MELM models generally produce less accurate simulations of physical production results as compared to production models that include both a mask process model and a lithography process model.
Thus, there is a need for a method, system, and software for IC inspection that enables enhanced mask inspection, and failure mode analysis.